Abstract: According to the power consumption problem existing in Δ∑delay locking ring modulator, a design method of class score points frequency Δ∑ delay locking ring is proposed. Through the use of separate frequency device, the working frequency of the Δ∑ delay locking ring modulator, charge pump and phase selector module is reduced, thus the difficulty of the design is decreased, and the traditional structure of the power and phase transition modulator deburring problem is solved. Meanwhile, the reference multiphase clock and FIR noise filter technology are adopted to solve the problem of phase illegibility and the deterioration of the quantization noise when separate frequency device is used. The results of the test show that the structure can realize 1ps lower temporal resolution with low frequency, and obtain the clock jitter performance as much as that of traditional structure.